Vhdl Language
Vhdl LanguageVHDL, the VHSIC (Very-High-Speed Integrated Circuit) Hardware Description Language is a language initially designed for documenting the internals of ASICs. It has since been adapted and extended for the design of new ASICs.
The language syntax is based on that of AdaLanguage, with extensions to deal with the asynchronous nature of hardware designs.
For example, this is how a simple 4-bit counter can be specified in VHDL (note that this example may contain bugs or syntax errors. This is all written from memory and it's quite a while since I last wrote any VHDL):
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- the interface of the counter
entity counter is
port(
CLK: in std_logic;
RST: in std_logic;
O: out std_logic_vector(3 downto 0));
end entity;
-- the rtl architecture of the entity. One entity can have multiple
-- architectures, the appropriate architecture being selected at
-- instantation.
architecture rtl of counter is
signal value: std_logic_vector(3 downto 0);
begin
-- sequential process
process (CLK,RST)
begin
-- reset logic
if (RST = '1') then
value <= (others => '0');
-- increment counter on the rising edge of the clock
elsif (rising_edge(CLK)) then
value <= value + 1;
end if;
end process;
-- concurrent statement to output the counter value
O <= value;
end rtl;
When synthesised this results in a hardware description that can be loaded into a ProgrammableLogic? device or etched into silicon.
One of the many traps for the unwary with VHDL is that not every construct is readily synthesisable. Sometimes an alternative way must be found to describe something to avoid using 90% of the target for a simple FIFO.
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(last edited October 8, 2006)
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