Power Pc

Note: This page has a lot of out-of-date information; even as of 11/2001 (when it was last edited). I'm going through to correct some of the anachronisms..... engineer_scotty (Scott Johnson)

The chip used in a PowerMac and the IBM eServer pSeries (RS/6000). A very close variant of PowerPc is also used in the IBM eServer iSeries (AS/400).

Why is a PowerPc faster than an Intel PIII for the same clock speed ?

AltiVec is one reason. Better architecture is another. I suggest reading Apple's rather accurate propaganda on it at http://www.apple.com -- MatthewTheobalds

Of course, the really cool thing about AltiVec is that it is everything MMX should have been. It can do SIMD processing like MMX, but it can also do streaming like SSE, and it can do all of that with floating point numbers like 3dNow.

I just saw a new ad from Apple claiming 3 gigaflops out of their Cube machine. The fastest Intel chip, to my understanding, hangs at just under 1 gigaflop. That said, the average person doesn't use that many flops. Rather, they stress the integer portion of the CPU, and the IO performance.

SJ: For office and multimedia applications; that's true. Games (3D ones), on the other hand, exercise heavily the floating point capabilities of a CPU, even with modern graphics accelerators.

AltiVec, while cool is only a small part of the reason, since Altivec is in only a very small number of installed systems, yet every PPC chip outperforms an equivalent Intel/AMD chip.

The reason is better architecture. The majority of PPC instructions execute in one clock cycle. Not as many instructions execute that quickly on the x86 platform.

This bit (which has long been a point of contention in RiscVsCisc), is way out of date. Ever since the 486, the x86 family has had pipelines; since the Pentium, the x86 architecture has had superscalar operation. The 386 was the last member in the family to average several cycles per instruction; Pentiums of any stripe can do more than one instruction per cycle.

Now, I've not done much low-level programming on PPCs, so I'm extrapolating from general RiscVsCisc arguments (although, I don't really know of any cases where a ReducedInstructionSetComputer chip goes against an Intel chip of the same speed and loses. It's just that Intel has such high clock speeds).

Intel's biggest advantage is its process technology and tooling. Not many semiconductor houses have access to 2Ghz+ dynamic logic; and Intel's feature sizes are also much smaller than most competitors. One exception, of course, is IBM; who have semiconductor technology and capacity to match (or even) exceed Intel. This is one area where Motorola has been lagging; and one reason that Intel architectures took the lead over PowerPC on the performance curve.

First, I'd be shocked if the PPC chip had less that 32 general integer registers. 32 general integer, 32 general FP. In comparison, an x86 chip has 4 general integer registers (8 with bit shifting and 16 bit integers). That means that an Intel chip has to spend more clock cycles shuffling stuff into and out of memory. Best case, the data is in the level 1 cache, so a memory transfer takes one cycle. Worst case, the data is only in RAM, so a memory transfer takes 10 clock cycles. PPC chips have the same memory transfer times, but with the extra registers, then can do less memory transferring.

Agreed

Another reason the PPC chips are faster is because almost every instruction executes in one clock cycle. On x86 platforms, many instructions take more that one cycle, although that is slowly changing with each new generation. Again, see above. Actually, many instructions on both architectures take several cycles; integer mult and div are notoriously slow. But with multiple pipelines; this is less of an issue.If your multiplier takes 3 cycles but has a 3-stage pipeline, you can still theoretically achieve 1 mult/second.

I've heard a few places that the PPC chip has a better instruction set. I'm not sure how much this really effects the tasks normal programs do, since I've mainly heard that argument in the context of special things like crypto processing.

PPC has a couple of cool bit twiddling operations likely useful in crpyto. But probably not a factor in the general case.

ArsTechnica has a great series of articles about the differences between PowerPc and Pentium chips.

Intel architecture has lots of other baggage it must carry around, due to backwards compatibility issues. Among them:

The rather baroque 4-layer protection mechanism. Any OS use all four "rings"? I've heard of one (OS/2?) that used three of the four rings; but most OS's only use ring 0 (most privilege) and ring 3 (least privilege)
Real mode and v86 mode. Needed to run DOS and win9x (and virtual DOS windows); now that WinXP has finally removed all traces of DOS; is this still necessary???
Integrated instruction and data cache. Back in the old days of DOS on the 8086/8088; game writers would write SelfModifyingCode (such as CompiledBitmaps? and similar techniques) to squeeze every cycle of performance out of the 8Mhz processor. When Intel added caching to the x86 family, they quickly realized that a separate I and D cache, like every other processor these days has, would break with self modifying code. So they designed an integrated cache that allows a RealProgrammer to modify an instruction on one clock cycle, fetch it on the next, and never touch memory. Quite an accomplishment, but a waste of gates. [With use of Java and .NET code that gets run through a JIT compiler, is this a waste or a benefit?]

And these (and other) legacy features lead to one of the Intel architecture's biggest problems; power consumption. PowerPcs don't need heatsinks the side of bricks, zillions of fans, or any of the other ways that Intel (as well as AMD and other x86-clone makers) use to cool CPUs that consume more power than some light bulbs out there.

Of course, given the legacy baggage aforementioned, it is a testament to the quality of Intel's engineers that they have been able to keep x86 alive - and at or near the top of the performance curve - for so long.

One major annoyance with the PowerPc is that the usual convention for assigning numbers to bits is backwards. In PowerPc collateral, bit 0 is the MSB, and bit 31 is the LSB (on a 32-bit architecture). Thank IBM for that bit of BrainDeath?...

CategoryHardware