Peripheral Processors

The Control Data (CDC) computer architecture of 1962 comprised a magnetic-core central memory accessible to one or two central arithmetic processors and ten or twenty peripheral processors (PPU). The memory design was such that the same modules were used to make up central and peripheral memory. Only the PPU could access the outer world via data channels, thus they were responsible for all input and output. The machine had no hardware interrupts, so device servicing was entirely based on polling device statuses. The PPU addressable word was 12 bits wide. Each PPU could perform device data transfers on 12 bits in parallel, either from a data register or from PPU memory. The size of the PPU was exactly 4096 words. The PPU could transfer data to central memory 60 bits parallel (5 PPU words at a time).

See http://research.microsoft.com/users/gbell/craytalk/ for a good overview of the CDC computers.